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TSMC and Chip Design Firms Use AI to Cut Energy Use in Next-Gen Chips

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The chips powering artificial intelligence consume enormous amounts of electricity, but Taiwan Semiconductor Manufacturing Co (TSMC), the world’s largest contract chipmaker, unveiled new efforts on Wednesday to make them more efficient—by using AI-powered software in the chip design process.

Speaking at a Silicon Valley conference, TSMC showcased strategies it says could boost the energy efficiency of AI chips by as much as 10 times.

Nvidia’s flagship AI servers, for instance, can draw up to 1,200 watts under heavy workloads—comparable to the electricity used by 1,000 U.S. homes if run continuously. TSMC’s approach centers on a new generation of chiplet-based designs, where multiple smaller chips made with different technologies are packaged together to function as a single processor.

To enable these designs, chipmakers are increasingly turning to AI-driven software tools. Partners like Cadence Design Systems and Synopsys debuted new products on Wednesday, built in close collaboration with TSMC. These tools have shown they can outperform human engineers in solving complex design problems—and in a fraction of the time.

“That helps to max out TSMC technology’s capability, and we find this is very useful,” said Jim Chang, deputy director of TSMC’s 3DIC Methodology Group. “This thing runs five minutes while our designer needs to work for two days.”

Still, physical constraints remain. As chips scale up, moving data on and off them via traditional electrical connections is reaching its limits. New approaches, such as optical interconnects to transfer information between chips, must be made reliable enough for deployment in massive data centers.

“Really, this is not an engineering problem,” said Kaushik Veeraraghavan, an engineer at Meta’s infrastructure group during his keynote. “It’s a fundamental physical problem.”

Synopsys Shares Plunge 35% on China Woes, Erasing 2025 Gains

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Synopsys shares tumbled nearly 35% on Wednesday, putting the chip design software giant on track for its worst single-day drop on record and wiping out gains accumulated in 2025. The decline followed disappointing earnings and fresh concerns about its business in China, a key semiconductor market under tightening U.S. export restrictions.

The company reported Q3 revenue of $1.74 billion, missing analyst estimates, with weakness in its IP segment. CEO Sassine Ghazi blamed U.S. export curbs — which blocked sales of chip design software to China for more than a month — and setbacks at a “major foundry customer.” Although restrictions were lifted in July, analysts said Chinese customer confidence has eroded, leaving demand subdued.

Synopsys generates more than 10% of industry revenue from China, but geopolitical tensions have made that stream increasingly fragile. Shares of rival Cadence Design Systems also dropped nearly 7% in sympathy.

While Ghazi did not identify the foundry customer, analysts pointed to Intel, which has dramatically scaled back its 18A chip manufacturing technology and broader foundry ambitions. J.P. Morgan suggested Synopsys had dedicated significant IP resources to Intel’s program, only to see its potential curtailed.

The downturn comes as Synopsys completes its $35 billion acquisition of Ansys, a move aimed at diversifying its engineering software portfolio. However, the company also announced it will cut 10% of its workforce by 2026 as part of a strategic review.

With trade restrictions clouding its China outlook and reliance on slowing customers like Intel, Synopsys faces mounting pressure to stabilize its core business even as it integrates Ansys.

Synopsys Misses Q3 Revenue Estimates, Shares Plunge 18%

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Chip design software provider Synopsys (SNPS.O) reported third-quarter revenue that fell short of Wall Street expectations, dragged down by weakness in its Design IP business, sending its stock down nearly 18.5% after hours.

Results and Outlook

  • Q3 Revenue: $1.74 billion vs. $1.77 billion expected (LSEG data)

  • Adjusted EPS: $3.39 vs. $3.74 expected

  • Q4 Guidance: $2.23–$2.26 billion revenue (above $2.09 billion consensus)

Key Pressures

  • Design IP Weakness: Includes interface, security, and embedded processor IP, plus implementation services.

  • Deal Fallout: Several deals failed to close due to:

    • U.S. export restrictions on China disrupting design starts

    • A major foundry customer canceling projects amid market and client-related challenges

  • CEO Sassine Ghazi: Said Synopsys had invested heavily in building IP for the foundry, but returns expected in 2H 2025 will now not materialize.

Strategic Moves

  • Ansys Acquisition: Completed $35B cash-and-stock purchase of engineering design firm Ansys in July after global antitrust reviews, including conditional approval in China.

  • Customer Base: Partners include Nvidia, Intel, and Qualcomm, among others.

Market Context

  • Rival Cadence Design Systems (CDNS.O): Raised its 2025 sales and profit forecast in July, highlighting diverging performance in the EDA software sector.

  • Synopsys’ miss underscores ongoing geopolitical risks and dependence on key customers in a competitive industry where regulatory headwinds are reshaping chip design markets.