TSMC and Chip Design Firms Use AI to Cut Energy Use in Next-Gen Chips
The chips powering artificial intelligence consume enormous amounts of electricity, but Taiwan Semiconductor Manufacturing Co (TSMC), the world’s largest contract chipmaker, unveiled new efforts on Wednesday to make them more efficient—by using AI-powered software in the chip design process.
Speaking at a Silicon Valley conference, TSMC showcased strategies it says could boost the energy efficiency of AI chips by as much as 10 times.
Nvidia’s flagship AI servers, for instance, can draw up to 1,200 watts under heavy workloads—comparable to the electricity used by 1,000 U.S. homes if run continuously. TSMC’s approach centers on a new generation of chiplet-based designs, where multiple smaller chips made with different technologies are packaged together to function as a single processor.
To enable these designs, chipmakers are increasingly turning to AI-driven software tools. Partners like Cadence Design Systems and Synopsys debuted new products on Wednesday, built in close collaboration with TSMC. These tools have shown they can outperform human engineers in solving complex design problems—and in a fraction of the time.
“That helps to max out TSMC technology’s capability, and we find this is very useful,” said Jim Chang, deputy director of TSMC’s 3DIC Methodology Group. “This thing runs five minutes while our designer needs to work for two days.”
Still, physical constraints remain. As chips scale up, moving data on and off them via traditional electrical connections is reaching its limits. New approaches, such as optical interconnects to transfer information between chips, must be made reliable enough for deployment in massive data centers.
“Really, this is not an engineering problem,” said Kaushik Veeraraghavan, an engineer at Meta’s infrastructure group during his keynote. “It’s a fundamental physical problem.”