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Nobel Laureate and Tech Giants Form Alliance to Build Mass-Produced Quantum Supercomputers

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Nobel Prize-winning physicist John M. Martinis has teamed up with Hewlett Packard Enterprise (HPE) and leading semiconductor companies to launch an ambitious initiative to build the world’s first mass-producible quantum supercomputer.

The collaboration, called the Quantum Scaling Alliance, brings together Applied Materials, Synopsys, 1QBit, Quantum Machines, Riverlane, and the University of Wisconsin. Its goal is to transition quantum computing from bespoke, laboratory-scale devices into scalable systems that can be manufactured using the same industrial tools that produce millions of chips for smartphones, laptops, and AI servers.

“Quantum chips have been made in an artisanal way for decades — small batches, one at a time. Now it’s time to move to a standard professional model,” Martinis told Reuters.

Quantum computers exploit qubits, which can exist in multiple states simultaneously, enabling them to perform complex calculations exponentially faster than traditional machines. The alliance aims to overcome one of the key barriers in the field — scaling quantum systems while maintaining stability and error correction.

HPE’s quantum team, led by Masoud Mohseni, is working on the integration of quantum and classical computing systems — a critical step toward achieving large-scale, fault-tolerant quantum machines.

“People think that once you have hundreds or thousands of qubits, you can easily scale to millions. That’s just not true. Each scale brings new challenges,” Mohseni explained.

By uniting expertise in chip manufacturing, software design, and computing architecture, the Quantum Scaling Alliance hopes to create the foundation for commercially viable quantum supercomputers — machines capable of tackling problems in chemistry, medicine, materials science, and cryptography that are currently beyond reach.

TSMC and Chip Design Firms Use AI to Cut Energy Use in Next-Gen Chips

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The chips powering artificial intelligence consume enormous amounts of electricity, but Taiwan Semiconductor Manufacturing Co (TSMC), the world’s largest contract chipmaker, unveiled new efforts on Wednesday to make them more efficient—by using AI-powered software in the chip design process.

Speaking at a Silicon Valley conference, TSMC showcased strategies it says could boost the energy efficiency of AI chips by as much as 10 times.

Nvidia’s flagship AI servers, for instance, can draw up to 1,200 watts under heavy workloads—comparable to the electricity used by 1,000 U.S. homes if run continuously. TSMC’s approach centers on a new generation of chiplet-based designs, where multiple smaller chips made with different technologies are packaged together to function as a single processor.

To enable these designs, chipmakers are increasingly turning to AI-driven software tools. Partners like Cadence Design Systems and Synopsys debuted new products on Wednesday, built in close collaboration with TSMC. These tools have shown they can outperform human engineers in solving complex design problems—and in a fraction of the time.

“That helps to max out TSMC technology’s capability, and we find this is very useful,” said Jim Chang, deputy director of TSMC’s 3DIC Methodology Group. “This thing runs five minutes while our designer needs to work for two days.”

Still, physical constraints remain. As chips scale up, moving data on and off them via traditional electrical connections is reaching its limits. New approaches, such as optical interconnects to transfer information between chips, must be made reliable enough for deployment in massive data centers.

“Really, this is not an engineering problem,” said Kaushik Veeraraghavan, an engineer at Meta’s infrastructure group during his keynote. “It’s a fundamental physical problem.”

Synopsys Shares Plunge 35% on China Woes, Erasing 2025 Gains

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Synopsys shares tumbled nearly 35% on Wednesday, putting the chip design software giant on track for its worst single-day drop on record and wiping out gains accumulated in 2025. The decline followed disappointing earnings and fresh concerns about its business in China, a key semiconductor market under tightening U.S. export restrictions.

The company reported Q3 revenue of $1.74 billion, missing analyst estimates, with weakness in its IP segment. CEO Sassine Ghazi blamed U.S. export curbs — which blocked sales of chip design software to China for more than a month — and setbacks at a “major foundry customer.” Although restrictions were lifted in July, analysts said Chinese customer confidence has eroded, leaving demand subdued.

Synopsys generates more than 10% of industry revenue from China, but geopolitical tensions have made that stream increasingly fragile. Shares of rival Cadence Design Systems also dropped nearly 7% in sympathy.

While Ghazi did not identify the foundry customer, analysts pointed to Intel, which has dramatically scaled back its 18A chip manufacturing technology and broader foundry ambitions. J.P. Morgan suggested Synopsys had dedicated significant IP resources to Intel’s program, only to see its potential curtailed.

The downturn comes as Synopsys completes its $35 billion acquisition of Ansys, a move aimed at diversifying its engineering software portfolio. However, the company also announced it will cut 10% of its workforce by 2026 as part of a strategic review.

With trade restrictions clouding its China outlook and reliance on slowing customers like Intel, Synopsys faces mounting pressure to stabilize its core business even as it integrates Ansys.