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Intel to unveil Panther Lake chip details, its first built entirely on 18A process

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Intel plans to reveal the technical architecture of its upcoming laptop chip, Panther Lake, on Thursday, according to sources cited by Reuters. The disclosure aims to reassure investors about Intel’s progress on its long-awaited 18A manufacturing process, the company’s next-generation technology platform developed after years of costly setbacks.

The Panther Lake chips will serve as Intel’s high-end mobile processors, featured in premium laptops. They are the first large-scale products built entirely using 18A — a key milestone as Intel seeks to reclaim market share lost to AMD and TSMC. The chipmaker conducted in-depth technical briefings and factory tours last week in Arizona, showcasing the redesigned architecture, including the AI engine, graphics cores, and media processing unit optimized for 18A.

According to those briefed, Panther Lake offers 30% better energy efficiency and up to 50% greater data processing power compared to its predecessor, Lunar Lake — a chip largely produced by TSMC. Intel executives said the new processors are expected to debut in early 2026.

The Arizona event underscored how vital Panther Lake is to Intel’s turnaround. The company reported a $2.9 billion loss in the second quarter and warned that future investments in its 14A process depend on finding new customers. Following political and financial turbulence — including President Trump’s call for CEO Lip-Bu Tan’s resignation and subsequent investments from SoftBank and Nvidia — Intel is under pressure to deliver results.

The Fab 52 facility in Arizona, built under former CEO Pat Gelsinger’s global expansion strategy, now houses the 18A process, featuring a new transistor design and more efficient power delivery. Intel did not disclose yield rates for Panther Lake, though previous reports indicate the success rate has improved from 5% to about 10% this year.

Taiwan Weighs High-Tech Strategic Partnership with the U.S. Amid Tariff Talks

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Taiwan is considering the creation of a high-tech strategic partnership with the United States, as Washington seeks greater Taiwanese investment and industrial cooperation, Taiwan’s top tariff negotiator said on Thursday.

Taiwan — home to the world’s leading contract chip manufacturer, TSMC — currently faces a 20% U.S. tariff on its exports and is looking to negotiate a reduction. The initiative comes as both economies explore deeper technological collaboration amid growing global competition over semiconductor supply chains.

Vice Premier Cheng Li-chiun, who heads Taipei’s delegation in the ongoing tariff talks, said she remains optimistic about reaching a consensus with the U.S. on what she called a “Taiwan model” for investment.

“The current negotiation focus is that the United States expects us to expand investments and engage in supply chain cooperation,” Cheng told reporters in Taipei after returning from Washington.

She emphasized that Taiwan’s approach would not involve relocating its core supply chains, but rather expanding production capacity on U.S. soil in strategic sectors. The plan would include export credit guarantees, joint R&D projects, and the co-development of industrial clusters between the two countries.

TSMC’S ROLE AND THE U.S. EXPECTATIONS

While the U.S. has expressed interest in more domestic semiconductor production, Cheng clarified that TSMC was not directly involved in the latest negotiation round. The company, currently investing $165 billion in chip plants in Arizona, continues to keep most of its production operations in Taiwan.

She also dismissed recent reports that U.S. Commerce Secretary Howard Lutnick had proposed a 50-50 chip production split, saying:

“That idea was not raised in our talks, and it is not something Taiwan would agree to.”

Cheng noted that Washington’s priority appears to be strengthening its domestic chip production to reduce supply chain dependence on Asia, while Taiwan’s long-term strategy is to stay rooted at home but expand globally through bilateral cooperation.

INDUSTRIAL PARTNERSHIP, NOT RELOCATION

The envisioned “Taiwan model,” Cheng said, represents a strategic partnership framework—one where the island’s companies would invest in R&D and manufacturing capacity abroad, supported by governmental financial and policy mechanisms, without shifting their operational core from Taiwan.

Neither the U.S. Commerce Department nor the Office of the U.S. Trade Representative has commented publicly on the discussions, which continued as the U.S. government entered a temporary shutdown this week.

With Taiwan’s semiconductor industry playing a pivotal role in the global AI and electronics boom, both Taipei and Washington are looking to balance national security priorities with economic growth.

“Our aim,” Cheng concluded, “is to remain rooted in Taiwan, deploy around the world, and build bilateral strategic cooperation that supports both sides’ technological ambitions.”

TSMC and Chip Design Firms Use AI to Cut Energy Use in Next-Gen Chips

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The chips powering artificial intelligence consume enormous amounts of electricity, but Taiwan Semiconductor Manufacturing Co (TSMC), the world’s largest contract chipmaker, unveiled new efforts on Wednesday to make them more efficient—by using AI-powered software in the chip design process.

Speaking at a Silicon Valley conference, TSMC showcased strategies it says could boost the energy efficiency of AI chips by as much as 10 times.

Nvidia’s flagship AI servers, for instance, can draw up to 1,200 watts under heavy workloads—comparable to the electricity used by 1,000 U.S. homes if run continuously. TSMC’s approach centers on a new generation of chiplet-based designs, where multiple smaller chips made with different technologies are packaged together to function as a single processor.

To enable these designs, chipmakers are increasingly turning to AI-driven software tools. Partners like Cadence Design Systems and Synopsys debuted new products on Wednesday, built in close collaboration with TSMC. These tools have shown they can outperform human engineers in solving complex design problems—and in a fraction of the time.

“That helps to max out TSMC technology’s capability, and we find this is very useful,” said Jim Chang, deputy director of TSMC’s 3DIC Methodology Group. “This thing runs five minutes while our designer needs to work for two days.”

Still, physical constraints remain. As chips scale up, moving data on and off them via traditional electrical connections is reaching its limits. New approaches, such as optical interconnects to transfer information between chips, must be made reliable enough for deployment in massive data centers.

“Really, this is not an engineering problem,” said Kaushik Veeraraghavan, an engineer at Meta’s infrastructure group during his keynote. “It’s a fundamental physical problem.”